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Ordering number: EN 5550
LC86P4164
CMOS LSI
LC86P4164 8-bit Single Chip Microcontroller
Overview
The LC86P4164 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC864100 series. This microcontroller has the function and the pin description of the LC864100 series mask ROM version, and the 64K-byte PROM. It is suitable for developing programs.
Package Dimensions
unit : mm
3128-DIP52S
[LC86P4164]
SANYO : DIP52S
Features
(1) Option switching by PROM data The option function of the LC864100 series can be specified by the PROM data. The functions of the trial pieces can be evaluated using the mass production board. (2) Internal PROM capacity : 65512 bytes (for program data) : 8192 x 12 bits (for character data) (3) Internal RAM capacity : 384 bytes
Mask ROM version LC864164 LC864156 LC864148 LC864140 LC864132 LC864124 LC864120 LC864116 LC864112 PROM capacity 65512 bytes 57344 bytes 49152 bytes 40960 bytes 32768 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes RAM capacity 384 bytes 384 bytes 384 bytes 384 bytes 384 bytes 384 bytes 384 bytes 384 bytes 384 bytes
(4) (5) (6) (7) (8)
Operating supply voltage : 4.5 V to 5.5 V Instruction cycle time : 1.0 s to 30 s Operating temperature : -30C to +70C The pin and the package compatible with the LC864100 series mask ROM devices Applicable mask ROM version : LC864164/LC864156/LC864148/LC864140/LC864132 LC864124/LC864120/LC864116/LC864112 (9) Factory shipment : DIP52S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcontroller Development Dep.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
33098HA (II) No. 5550-1/20
LC86P4164
Usage Notes
The LC86P4164 is provided for the first release and small shipping of the LC864100 series. At using, take notice of the followings. (1) Differences between the LC86P4164 and the LC864100 series
Item Operation after reset releasing LC86P4164 The option is specified by degrees until 3 ms after going to a 'H' level to the reset terminal. The program is executed from 00H of the program counter. 4.5 V to 6.0 V -30 to +70C LC864164/56/48/40/32/24/20/16/12 The program is executed from 00H of the program counter immediately after going to a 'H' level to the reset terminal. 4.5 V to 6.0 V -30 to +70C
Operating supply voltage range (VDD) Operating temperature range (Topr) Power dissipation
Refer to 'electrical characteristics' on the semiconductor news.
The LC86P4164 uses the program memory area of 256 bytes from FF00H to FFFFH to select the options. (2) Option The option data is created by the option specified program "SU86K.EXE". The created option data is linked to the program area by the linkage loader "L86K.EXE". (3) ROM space The LC86P4164 and LC864100 series use the program memory area of 256 bytes from FF00H to FFFFH to select options. The program memory has 65280 bytes from 0000H to FEFFH.
13FFFFH 0FFFFH 0FF00H 0FEFFH 0DFFFH 0BFFFH 09FFFH 07FFFH 05FFFH Program area 64K bytes 0000H LC864164 LC864156 LC864148 LC864140 LC864132 LC864124 Program area 56K bytes Program area 48K bytes Program area 40K bytes Program area 32K bytes Program area 24K bytes Character generator ROM Option specified area 256 bytes Character generator ROM Option specified area 256 bytes Character generator ROM Option specified area 256 bytes Character generator ROM Option specified area 256 bytes Character generator ROM Option specified area 256 bytes Character generator ROM Option specified area 256 bytes
13FFFFH 0FFFFH
Character generator ROM Option specified area 256 bytes
Character generator ROM Option specified area 256 bytes
Character generator ROM Option specified area 256 bytes
04FFFH 03FFFH 02FFFH 0000H LC864120 LC864116 LC864112 Program area 20K bytes Program area 16K bytes Program area 12K bytes
No. 5550-2/20
LC86P4164
How to use
(1) Create a programming data for LC86P4164 Programming data for EPROM of the LC86P4164 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, SU86K.EXE. The HEX file is used as the programming data for the LC86P4164.
(2) How to program for the PROM The LC86P4164 can be programmed by the EPROM programmer with attachment; W86EP4164D. * Recommended EPROM programmer
Manufacturer Advantest Andou AVAL Minato electoronics EPROM progammer R4945, R4944 AF-9704 PKW-1100, PKW-3000 MODEL 1890A
*
"27010 (Vpp=12.5V) Intel high speed programming" mode should be adopted. The address must be set to "0 to 13FFFH" and a jumper (DASEC) must be set to 'OFF' at programming.
(3)
How to use the data security function "Data security" is the function to disable the EPROM data from being read out. The following is the procedure in order to execute the data security function. 1. Set 'ON' the jumper of attachment. 2. Program again. Then the EPROM programmer displays an error. The error means that the data security functions normally. It is not a trouble of the EPROM programmer or the LSI. Notes * Data security is not executed when the data of all address have 'FF' at the procedure 2 above. * Data security cannot be executed by programming the sequential operation "BLANK=>PROGRAM=>VERIFY" at procedure 2 above. * Set the jumper to 'OFF' after executing the data security.
Data security
Data security OFF
Jumper pin 1
Jumper
W86EP4164D
No. 5550-3/20
LC86P4164
Pin Assignment
P10/SO0 P11/SI0/SB0 P12/SCK0 P13 P14 P15 P16 P17/PWM DVSS CF1 CF2 DVDD P90/AN0 P91/AN1 P92/AN2 P93/AN3 RES LC1 LC2 FILT AVDD AVSS CVIN VS HS I
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 PWM9 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 BL B G R
Top view
No. 5550-4/20
LC86P4164
System Block Diagram
Interrupt control
IR
PLA A14 to A0 D7 to D0 TA CE OE DASEC
Standby control
PROM control
CF RC LC ACC
Colck generator
PROM(64KB)
PC
Bus interface
B register
SIO0
Port 1
C register
Timer 0
Port 7
ALU
Timer 1
ADC INT0 to INT3 Noise rejection filter
Port 9
PSW
Data slicer
RAR
PWM
PLL
RAM
Stack pointer OSD control circuit CGROM Port 0 VRAM Watchdog timer
No. 5550-5/20
LC86P4164
Pin Description
Pin name DVSS CF1 CF2 DVDD RES LC1 LC2 FILT AVDD AVSS CVIN VS HS I R G B BL Pin No. 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I/O -- I O -- I I O O -- -- I I I O O O O O Function description Negative power supply for digital circuit Input terminal for ceramic resonator Output terminal for ceramic resonator Positive power supply for digital circuit Reset terminal LC oscillation circuit input terminal LC oscillation circuit output terminal Filter terminal for PLL Positive power supply for analog circuit Negative power supply for analog circuit Video signal input terminal Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Image intensity control output Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption/ OSD image signal PWM0 to PWM9 output terminal 15V withstand 8-bit Input/output port 45 to 52 I/O Input/output can be specified in nibble unit HOLD release input Interrupt input Pull-up resistor Provided/not provided (in bit units) Output Format CMOS/Nch-OD (in bit units) Output Format CMOS/Nch-OD (in bit unit) D0 to D7 (*2) A4 (*1) A5 (*1) A6 (*1) A7 (*1) Option PROM mode
PWM0 to PWM9 Port 0 P00 to P07
31 to 40
O
PWM0 to PWM8 : A8 to A16 (*1) PWM9 : "L" fixed
Port 1 P10 to P17 1 to 8 I/O
8-bit Input/output port Input/output can be specified in bit unit. Other functions P10 P11 P12 P17 SIO0 data output SIO0 data input /bus input/output SIO0 clock input/output Timer 1 (PWM) output
Continued on next page.
No. 5550-6/20
LC86P4164
Continued from preceding page.
Pin name Port 7 P70 P71 to P73 Pin No. 41 42 to 44 I/O I/O I Function Description 4-bit input port Other functions P70 INT0 input/HOLD release input/ Nch-transistor output for watchdog timer INT1 input/HOLD release input INT2 input/timer 0 event input INT3 input (noise rejection filter attached input/timer 0 event input Option Pull-up resistor provided/ not provided (in bit units) PROM mode P70 : VPP (*3) P71 : DASEC (*4) P72 : OE (*5) P73 : CE (*6)
P71 P72 P73
Interrupt receiver format vector address Rising INT0 INT1 INT2 INT3 Port 9 P90 to P93 13 to 16 I enable enable enable enable Falling enable enable enable enable Rising/Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Vector 03H 0BH 13H 1BH A0 to A3 (*3)
4-bit input port Other function A/D converter input port (4 lines)
*1 *2 *3 *4 *5 *6
An Address input Data I/O Power for programming Memory select input/output for data security Output Enable input Chip Enable input All of port options except the 4-bit unit pull-up resistor option of Port 0 can be specified in a bit unit.
*
* Port status during reset
Terminal Port 0 Port 1 Port 7 I/O Input Input Input Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF Fixed pull-up resistor provided
*
AVDD and AVSS are the power supply terminals for built-in analog circuit while DVDD and DVSS are the power supply terminals for built-in digital circuit. Connect them like the following figure to reduce the mutual noise influence.
LSI Power Power Supply supply DVDD DVSS AVDD AVSS
No. 5550-7/20
LC86P4164
Specifications 1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Supply voltage Input voltage VDDmax VI(1) DVDD, AVDD * P71, 72, 73 * Port 9 * RES,HS,VS,CVIN R, G, B, BL, I, FILT PWM0 to PWM9 Ports 0, 1, P70 Ports 0, 1 * Pull-up MOS transistor output * At each pin * CMOS output * At each pin * CMOS output * At each pin The total of all pins The total of all pins The total of all pins At each pin At each pin At each pin The total of all pins The total of all pins The total of all pins The total of all pins Ta = -30 to +70C -30 -55 DVDD = AVDD min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
Output voltage
VO(1) VO(2)
-0.3 -0.3 -0.3 -2
VDD+0.3 +15 VDD+0.3 mA
Input/output voltage Highlevel output current Peak output current
VIO(1) IOPH(1)
IOPH(2) IOPH(3) Total output current IOAH(1) IOAH (2) IOAH (3) IOPL(1) IOPL(2) IOPL(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4)
Ports 0, 1 R, G, B, BL, I Port 1 Port 0 R, G, B, BL, I Ports 0, 1 P70 * R, G, B, BL, I * PWM0 to PWM9 Port 0 Port 1, P70 R, G, B, BL, I PWM0 to PWM9 DIP52S
-4 -5 -10 -10 -15 20 30 5 40 40 15 30 430 +70 +125 mW C
Lowlevel output current
Peak output current
Maximum power dissipation Operating temperature range Storage temperature range
Pd max Topr Tstg
*
DVSS and AVSS must be supplied the same voltage, VSS. DVDD and AVDD must be supplied the same voltage, VDD.
VSS = DVSS = AVSS VDD = DVDD = AVDD
No. 5550-8/20
LC86P4164
2. Recommended Operating Range at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Operating supply voltage range Hold voltage VDD DVDD, AVDD 0.98 s tCYC tCYC 1.02 s RAMs and the registers hold data at HOLD mode. Output disable Output disable 4.5 to 5.5 4.5 to 5.5 min 4.5 Ratings typ max 5.5 V Unit
VHD
DVDD, AVDD
2.0
5.5
Input high-level voltage
VIH(1) VIH(2)
Port 0 (Schmitt) * Port 1 (Schmitt) * P72,73 * HS,VS * P70 port input / interrupt * P71 * RES (Schmitt) P70 Watchdog timer input Port 9 port input Port 0 * Port 1 * P72,73 * HS,VS * Port 9 (Schmitt) (Schmitt)
0.6VDD 0.75VDD
VDD VDD
VIH(3)
Output N-channel transistor OFF
4.5 to 5.5
0.75VDD
VDD
VIH(4) VIH(5) Input low-level voltage VIL(1) VIL(2)
Output N-channel transistor OFF
4.5 to 5.5 4.5 to 5.5
VDD-0.5 0.7VDD VSS VSS
VDD VDD 0.2VDD 0.25VDD
Output disable Output disable
4.5 to 5.5 4.5 to 5.5
VIL(3)
N-channel transistor * P70 port input / OFF interrupt * P71 * RES (Schmitt) P70 Watchdog timer input Port 9 port input CVIN OSD function Except OSD function N-channel transistor OFF
4.5 to 5.5
VSS
0.25VDD
VIL(4) VIL(5) CVIN input amplitude Operation cycle time VCVIN tCYC(1) tCYC(2)
4.5 to 5.5 4.5 to 5.5 5.0 4.5 to 5.5 4.5 to 5.5
VSS VSS 0.7 0.98 0.98 1
0.6VDD 0.3VDD 2.3 1.02 30 Vp-p s
*
* Vp-p : Peak-to-peak voltage
No. 5550-9/20
LC86P4164
Parameter Symbol Pins Conditions VDD [V] Oscillation frequency range (Note 1) FmCF CF1, CF2 12MHz (ceramic resonator oscillation) Refer to Figure 1. 14.11MHz (LC oscillation) Refer to Figure 2. RC oscillation CF1, CF2 12 MHz (ceramic resonator oscillation) Refer to Figure 3. 4.5 to 5.5 min 11.76 Ratings typ 12 max 12.24 MHz Unit
FmLC
LC1, LC2
4.5 to 5.5
14.11
FmRC Oscillation stable time period (Note 2) tmsCF
4.5 to 5.5 4.5 to 5.5
0.4
0.8 0.02
2.0 0.2 ms
(Note 1) (Note 2)
The oscillation constant is shown on Table 1 and Table 2. The oscillation stable time period means the time to oscillate stably after the following conditions. 1. Supplying voltage. 2. Release the HOLD mode. 3. Release stopping the main-clock oscillation. Refer to Figure 3 for details.
No. 5550-10/20
LC86P4164
3. Electrical Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD[V] Input high-level current IIH(1) * Port 1 * Port 0 without pull-up MOS transistor * Output disable * Pull-up MOS transistor OFF * VIN = VDD (including the off-leak current of the output transistor) VIN = V DD 4.5 to 5.5 min Ratings typ max 1 A Unit
IIH(2)
* Port 7 without pull-up MOS transistor * Port 9 * RES * HS,VS * Port 1 * Port 0 without pull-up MOS transistor
4.5 to 5.5
1
Input low-level current
IIL(1)
* Output disable * Pull-up MOS transistor OFF * VIN = VSS (including the off-leak current of the output transistor) VIN = V SS
4.5 to 5.5
-1
IIL(2)
* Port 7 without pull-up MOS transistor * Port 9 * RES * HS,VS CMOS output of Ports 0,1 R, G, B, BL, I Ports 0, 1 Ports 0, 1
4.5 to 5.5
-1
IIL(3) Output high-level voltage VOH(1) VOH(2) Output low-level voltage VOL(1) VOL(2)
VIN = V SS I OH = -1.0 mA I OH = -0.1 mA I OL = 10 mA * IOL = 1.6 mA * The total current of the ports 0,1 is not over 40 mA * I OL = 30 mA * The current of any unmesurement pin is not over 3 mA. I OL = 1 mA VOH = 0.9 VDD
4.5 to 5.5 4.5 to 5.5
-1 VDD-1 V
4.5 to 5.5 VDD-0.5 4.5 to 5.5 4.5 to 5.5 1.5 0.4
VOL(3)
* R, G, B, BL, I * PWM0 to PWM9
4.5 to 5.5
0.4
VOL(4) Pull-up MOS transistor resistance Output offleakage current Hysteresis voltage Rpu
P70 * Ports 0,1 * Port 7 PWM0 to PWM9
4.5 to 5.5 4.5 to 5.5 13 38
0.4 80 k
IOFF
VOUT = 13.5 V
4.5 to 5.5
5
A
VHIS
* * * *
Ports 0,1 Port 7 RES HS,VS
Output disable
4.5 to 5.5
0.1 VDD
V
No. 5550-11/20
LC86P4164
Parameter Symbol Pins Conditions VDD [V] Input clamp voltage Pin capacitance VCLMP CP CVIN All pins * f = 1 MHz * Unmeasured input pins are set to VSS level. * Ta = 25C 5.0 4.5 to 5.5 min 2.3 Ratings typ 2.5 10 max 2.7 V pF Unit
4. Serial Input/Output Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD[V] Cycle Lowlevel pulse width Highlevel pulse width Cycle tCKCY (1) tCKCY (1) * SCK0 * SCLK0 Refer to Figure 5. 4.5 to 5.5 4.5 to 5.5 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKCY (1)
4.5 to 5.5
1
Serial clock
tCKCY (2) tCKCY (2)
Output clock
Lowlevel pulse width Highlevel pulse width
* SCK0 * SCLK0
* Use a pull-up resistor (1 k) during open drain output * Refer to Figure 5.
4.5 to 5.5 4.5 to 5.5
2 1/2tCKCY
tCKCY (2)
4.5 to 5.5
1/2tCKCY
Serial input
Data set-up time Data hold time Output delay time (External serial clock) Output delay time (Internal serial clock)
tICK tCKI
SI0
* Data set-up to SCK0 rising * Data hold from SCK0 rising * Refer to Figure 5. * Use a pull-up resistor (1 k) during open drain output. * Data set-up to SCK0 falling * Data hold from SCK0 falling * Refer to Figure 5.
4.5 to 5.5 4.5 to 5.5
0.1 0.1
s
tCKO(1)
SO0
4.5 to 5.5
7/12tCYC +0.2
s
Serial output
tCKO(2)
4.5 to 5.5
1/3tCYC +0.2
No. 5550-12/20
LC86P4164
5. Pulse Input Conditions at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] High/low level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) * INT0,INT1 * INT2/T0IN * Interrupt acceptable * Timer0-countable 4.5 to 5.5 4.5 to 5.5 min 1 2 Ratings typ max tCYC Unit
* Interrupt acceptable INT3/T0IN * Timer0-countable (The noise rejection clock is selected to 1/1) * Interrupt acceptable INT3/T0IN * Timer0-countable (The noise rejection clock is selected to 1/16) RES HS, VS Reset acceptable Display position controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 7. Refer to Figure 7. The monitor point in Figure 10 is 1/2 VDD.
tPIH(3) tPIL(3)
4.5 to 5.5
32
tPIL(4) tPIH(5)
4.5 to 5.5 4.5 to 5.5
200 10
s tCYC
tPIL(5)
Rising/falling time Horizontal pull-in range
tTHL tTLH FH
HS HS
4.5 to 5.5 4.5 to 5.5 15.23 15.73
500 16.23
ns kHz
6. A/D Converter Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Conversion time Reference current Analog input voltage range Analog port input current N ET tCAD IREF VAIN IAINH IAINL AN0 to AN3 VAIN = VDD VAIN = V SS From selecting Vref to resulting (Note 3) 1 bit conversion time = 2tCYC (Regulate the ladder resistor) 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 -1 VSS 1.0 min 4 1/4 1/2 1.96 2.0 V DD 1 Ratings typ max bit LSB s mA V A Unit
(Note 3) Absolute precision excepts quantizing error (1/2 LSB).
No. 5550-13/20
LC86P4164
7. Current Dissipation Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current dissipation during basic operation (Note 4) IDDOP(1) DVDD, AVDD * FmCF = 12 MHz Ceramic resonator oscillation * FmLC = 14.11 MHz LC oscillation * System clock : CF oscillation * Internal RC oscillation stops * HALT mode * FmCF = 12 MHz Ceramic resonator oscillation * FmLC = 0 Hz (oscillation stops) * System clock : CF oscillation * Internal RC oscillation stops. * HALT mode * FmCF = 0 MHz (oscillation stops) * FmLC = 0 Hz (oscillation stops) * System clock : Internal RC * HOLD mode * All oscillation stops. 4.5 to 5.5 min Ratings typ 21 max 32 mA Unit
Current dissipation in HALT mode (Note 4)
IDDHALT(1)
DVDD, AVDD
4.5 to 5.5
5
10
mA
I DDHALT (2)
DVDD, AVDD
4.5 to 5.5
400
800
A
Current dissipation in HOLD mode (Note 4)
I DDHOLD
DVDD, AVDD
4.5 to 5.5
0.05
20
A
(Note 4)
The currents of the output transistors and the pull-up MOS transistors are ignored.
No. 5550-14/20
LC86P4164
Oscillation type 12 MHz ceramic resonator oscillation Kyocera Manufacturer Murata Oscillator CSA12.0MTZ CST12.0MTW KBR-12.0M 47 pF C1 33 pF on chip 47 pF C2 33 pF
* Both C1 and C2 must use an K rank (10%) and an SL characteristics. Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)
Oscillation type 14.11 MHz LC oscillation
L 5.6 H 4.7 H 10% (Variable)
C3 27 pF 27 pH
C4 30 pF (Trimmer) 27 pH
* See Figure 11,12. Table 2. LC Oscillation Guaranteed Constant (OSD clock)
(Notes)
* Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. * If you use other oscillators than those shown above, we provide no guarantee for the characteristics. * Adjust the voltage of monitor point in Figure 10 to 1/2VDD 10% by the LC oscillation constant 'L' or 'C' to lock the PLL circuit.
CF1
CF2
LC1
LC2
LC1
LC2
C1
CF
C2
C3
L
C4
C3
L
C4
Main clock
Figure 1 Ceramic Resonator Oscillation Figure 2
OSD clock
LC Resonator Oscillation
No. 5550-15/20
LC86P4164
VVDD DD VVDD lowerlimit DD lower limit 0V 0V
Reset time
Power supply
RES
Internal RC resonator oscillation CF1, CF2
tmsCF
Operation mode
Unfixed
Reset
Instruction execution mode

HOLD release signal
Valid
Internal RC resonator oscillation CF1, CF2
tmsCF
Operation mode
HOLD
Instruction execution mode

Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES (Note) Set the values of CRES, RRES so that (Note) Fix value of CRES, RRES that is sure to the reset time 200 s,s or longer. reset untill is 200 after Power supply has been over inferior limit of supply voltage.
Figure 4 Reset Circuit
No. 5550-16/20
LC86P4164
0.5VDD < AC timing point >
tCKCY tCKL
Serial clock
VDD
tCKH
1 k
tICK
Serial input
tCKI
tCKO
Serial output < Timing > 50pF
< T load > est
Figure 5 Serial Input/output Test Condition
tPIL
tPIH
Figure 6 Pulse Input Timing Condition - 1
tPIL (5)
HS 0.75VDD 0.25VDD HS
tPIH (5)
0.75VDD 0.25VDD
tTLH
tTHL
VS
tPIL (5)
VS more than 1tCYC
tPIH (5)
more than 1tCYC
(a) In case of active low
(b) In case of active high Figure 7 Pulse Input Timing Condition - 2
LC86P4164
10 k HS HS C536
Figure 8 Recommended Interface Circuit No. 5550-17/20
LC86P4164
Noise filter 470
C-Video
560pF 1F
CVIN
Coupling capacitor
Figure 9 CVIN Recommended Circuit
Monitor point
22k
FILT + 2.2F 1000pF
Figure 10 FILT Recommended Circuit
(Note)
* Place the parts connected to the FILT terminal at the shortest pattern length possible on the board.
LC oscillation frequency [MHz]
C = 30pF C = 33pF
LC oscillation frequency [MHz]
16
VDD = 5.0V L = 4.7H C = C3 = C4 Ta = 2 5 C
16
VDD = 5.0V C3 = C4 = 33pF Ta = 2 5 C
L = 4.5H L = 4.7H
15
C = 36pF C = 39pF
15
L = 4.9H L = 5.1H
14
14
13
13
0
1
2
3
4
5
0
1
2
3
4
5
FILT [V]
FILT [V]
Figure 11 FILT-LC Oscillation Frequency (1)
Figure 12 FILT-LC Oscillation Frequency (2)
No. 5550-18/20
LC86P4164
Requirements Prior to Mounting
Notes on Handling * The construction of one-time microcontrollers in which the PROM is not programmed precludes Sanyo from fully testing them before they are shipped. The screening procedure described below is recommended in order to attain higher reliability after programming the PROM. * The nature of one-time microcontrollers in which the PROM is not programmed precludes us from fully testing them by writing all of the bits. Therefore, it is not possible for us to guarantee a write yield of 100%. * Storage in moisture-proof packaging (unopened) While they are still in the moisture-proof packaging, these devices should be stored at a temperature of 30C and a humidity of no more than 70%. * After opening the moisture-proof packaging These devices should be mounted and soldered as soon as possible after the moisture-proof packaging is opened. Once the moisture-proof packaging is opened, the devices should be stored at a temperature of 30C and a humidity of no more than 70% for no more than 96 hours. a. In the case of models that are programmed by the user (models that are shipped with the PROM not programmed) DIP model
Programming/verification
Recommended screening procedure Exposure to high temperature without power 150 5C, 24 -0 hours
+1
Confirmation that program can be read
Mounting b. Requirements prior to mounting for models that are programmed by Sanyo (models that are shipped with the PROM already programmed) DIP model
Mounting
No. 5550-19/20
LC86P4164
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice.
PS No. 5550-20/20

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